Semiconductor devices are fabricated by depositing various material layers, such as conductors, semiconductors, and insulators, and patterning the various material layers to form circuit elements and interconnects therebetween. Some semiconductor devices are arranged in a matrix or array, such as is shown in the prior art perspective view of a semiconductor device 100 in FIG. 1. A plurality of cells 114 are arranged in an array of rows and columns, and a plurality of first conductive lines 112 and second conductive lines 116 running in a different direction than first conductive lines 112 are disposed below and above the array of cells 114, respectively, as shown. The cells 114 are selected by accessing the cells 114 through the first conductive line 112 and second conductive line 116 adjacent the particular cell 114. The cells 114 in the array 100 may comprise memory cells, fuses, or anti-fuses, as examples, although the cells 114 may alternatively comprise other devices or components, for example.
The first conductive lines 112 and second conductive lines 116 may comprise conductive or semiconductive materials, for example. The first conductive lines 112 may comprise a first layer 118 of polysilicon, for example, and a liner 120 disposed over the first layer 118. The liner 120 may comprise TiN, TiSx, or combinations thereof, although alternatively, the liner 120 may also comprise other materials. The plurality of cells 114 may comprise a first conductive layer 122, a cell region 124 disposed over the first conductive layer 122, and a second conductive layer 128 disposed over the cell region 124. The first conductive layer 122 and the second conductive layer 128 may comprise polysilicon, for example. The cell region 124 comprises a memory cell, a fuse, an anti-fuse, or may alternatively comprise other circuit elements.
A prior art method of forming an insulator between cell regions 114 of a semiconductor device 100 will next be described with reference to FIGS. 2 through 4, which show a semiconductor device 100 in a cross-sectional view at various stages of manufacturing. Referring first to FIG. 2, a workpiece 102 is provided. A plurality of first conductive lines 112 comprising polysilicon 118, for example, are formed over the workpiece 102. The first conductive lines 112 may be formed by first depositing a conductive material 118 over the workpiece 102, and depositing an optional liner 122 over the conductive material 118. A photoresist (not shown) is deposited over the optional liner 122 or conductive material 118, if a liner 122 is not used. The photoresist is then patterned, and the photoresist is used as a mask while exposed portions of the liner 122 and conductive material 118 are etched away, leaving the conductive lines 112 formed over the workpiece 102. Alternatively, the first conductive lines 112 may be formed using a damascene process, for example.
The material layers of the cell regions 114 are then deposited and patterned. For example, a first conductive layer 122 may be deposited over the patterned first conductive lines 112, and cell region material 124 is deposited over the first conductive layer 122. A second conductive layer 128 is deposited over the cell region material 124. The first conductive layer 122 and second conductive layer 128 may comprise polysilicon, for example, although other semiconductive or conductive materials may also be used. The second conductive layer 128, the cell region material 124, and the first conductive layer 122 are patterned to form a plurality of cells 114 disposed in an array of rows and columns. To form the cells 114, a photoresist (not shown) may be deposited over the second conductive layer 128, and the photoresist may be patterned with the cell 114 array pattern. The pattern of the photoresist is transferred to the underlying second conductive layer 128, cell region material 124, and first conductive layer 122 by using the photoresist as a mask while exposed portions of the second conductive layer 128, cell region material 124, and first conductive layer 122 are etched away.
High-density plasma (HDP) oxide is an insulator that is commonly used to isolate adjacent structures such as conductive lines 112 and cells 114. In the prior art insulator formation method shown, an HDP oxide 130 is deposited over the cells 114 and plurality of first conductive lines 112, as shown. One characteristic of HDP oxide 130 is that it forms peaks or huts 132 over taller features of the semiconductor device 100. These peaks 132 typically have the shape of a bishop's hat or miter, for example.
In order to make electrical contact to the second conductive layer 128 of the cells 114, the HDP oxide 130 may be removed from the top surface of the second conductive layer 128, as shown in FIG. 3. This may be accomplished by performing a chemical-mechanical polishing (CMP) process, which is adapted to stop on the top surface 136 of the second conductive layer 128. However, if the second conductive layer 128 material comprises polysilicon, which is often the case, the HDP oxide 130 is removed at a faster rate than the second conductive layer 128 material. This is problematic in that after the CMP process, the HDP oxide 130 may comprise a height 134 that is less than the height 136 of the second conductive layer 128. Typical oxide slurries used in CMP processes of the prior art may comprise a polysilicon 128 removal rate of about 4500 Å per minute, and an HDP oxide removal rate of about 2300 Å, for example. Therefore, the oxide-to-poly removal rate ratio may be about 0.51 in the prior art.
It is undesirable for the HDP oxide height 134 to be lower than the height 136 of the conductive material 128 between the cells 114 because this causes a lack of control of the thickness of subsequently formed second conductive lines 116, shown in FIG. 4. To form the second conductive lines 116, a second conductive line material is deposited over the second conductive material 128 of the cells 114. It is also undesirable to have an excess amount of the HDP oxide 130 removed because the CMP process can create defects in the top surface of the HDP oxide 130 between cell regions 114. These defects may include a concave structure of the top surface of the HDP oxide 130, microscratches in the top surface of the HDP oxide 130, and cracks within the HDP oxide 130, as examples.
Therefore, what is needed in the art is a method of forming an insulator between features of a semiconductor device, wherein the insulator is not recessed between adjacent features.